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1997, 2000 data sheet mos integrated circuit 8-bit single-chip microcontrollers m pd78f0058,78f0058y description the m pd78f0058 is a product of the m pd780058 subseries in the 78k/0 series and equivalent to the m pd780058 with a flash memory in place of internal rom. this device is incorporated with a flash memory which can be programmed without being removed from the substrate. the m pd78f0058y is a products based on the m pd78f0058, with an i 2 c bus interface supporting multimaster. functions are described in detail in the following users manuals, which should be read when carrying out design work. m pd780058, 780058y subseries users manual :u12013e 78k/0 series users manual instruction :u12326e features ? pin-compatible with mask rom version (except v pp pin) ? flash memory : 60 kbytes note 1 ? internal high-speed ram : 1024 bytes ? internal expansion ram : 1024 bytes note 2 ? buffer ram : 32 bytes ? power supply voltage : v dd = 2.7 to 5.5 v notes 1. the flash memory capacity can be changed with the memory size switching register (ims). 2. the internal expansion ram capacity can be changed with the internal expansion ram size switching register (ixs). remark for the differences between the flash memory versions and the mask rom versions, refer to 1. differences between m pd78f0058, 78f0058y, and mask rom version. application fields car audio systems, cellular phones, pagers, printers, av equipment, cameras, ppcs, vending machines, etc. the mark shows major revised points. document no. u12092ej1v0ds00 (1st edition) date published march 2000 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 ordering information part number package m pd78f0058gc-8bt 80-pin plastic qfp (14 14 mm) m pd78f0058gk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd78f0058gk-9eu note 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.0 mm) m pd78f0058ygc-8bt 80-pin plastic qfp (14 14 mm) m pd78f0058ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd78f0058ygk-9eu note 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.0 mm) note under development
3 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries name. pd780824 80-pin for automotive meter drive. on-chip dcan controller pd780814 pd78083 pd78044f 80-pin basic subseries for fip drive. display output total: 34 pd78044h 80-pin pd78044f with n-ch open drain i/o. display output total: 34 pd780232 80-pin for panel control. on-chip fip c/d. display output total: 53 pd780034a pd780024a pd780024ay pd78014h pd78018f 64-pin 64-pin 64-pin 64-pin pd780024a with enhanced a/d converter pd78018f with enhanced serial i/o emi-noise reduced version of the pd78018f basic subseries for control pd78018fy pd780034ay pd780078 64-pin pd780034a with timer and enhanced serial i/o pd780078y pd780208 pd780228 pd780308 pd78064b pd78064 pd780308y pd78064y 42/44-pin 100-pin 100-pin 100-pin 100-pin 100-pin lcd drive fip tm drive 78k/0 series on-chip uart, capable of operating at low voltage (1.8 v) pd78044f with enhanced i/o and fip c/d. display output total: 53 pd78044h with enhanced i/o and fip c/d. display output total: 48 pd780988 64-pin inverter control pd780841 80-pin call id on-chip inverter control circuit and uart. emi-noise reduced version. on-chip call id function, simplified dtmf. emi-noise reduced version. pd78064 with enhanced sio and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for lcd drive, on-chip uart pd780833y 80-pin on-chip j1850 (class2) controller pd78098b pd780701y pd780955 pd780852 80-pin 80-pin 80-pin 80-pin meter control bus interface pd78054 with iebus tm controller. emi-noise reduced version. on-chip dcan/iebus controller ultra low-power consumption. on-chip uart. on-chip controller/driver for automotive meter drive products under development products in mass production y subseries products supports the i 2 c bus. pd780065 80-pin pd780024a with expanded ram pd780058 pd78058f pd78054 80-pin 80-pin 80-pin pd78054 with enhanced serial i/o emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter and enhanced i/o 100-pin pd78078 pd78070a pd78075b 100-pin 100-pin 100-pin control pd78054 with timer and enhanced external interface emi-noise reduced version of the pd78078 rom-less version of the pd78078 pd78078y with enhanced serial i/o and limited functions pd78054y pd78058fy pd780058y pd780018ay pd78070ay pd78078y pd780948 100-pin on-chip dcan controller 64-pin special in dcan controller function pd780958 100-pin industrial meter control m m m m m m m m m m m m m m m m m m m m m m m m m mm m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m
4 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 the major functional differences among the subseries are listed below. function rom timer 8-bit 10-bit 8-bit serial i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a interface value expansion control m pd78075b 32 k to 40k 4 ch 1 ch 1 ch 1 ch 8 ch C 2 ch 3 ch (uart: 1 ch) 88 1.8 v ? m pd78078 48 k to 60k m pd78070a C 61 2.7 v m pd780058 24 k to 60 k 2 ch 3 ch (time-division 68 1.8 v uart: 1 ch) m pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780065 40 k to 48 k C 4 ch (uart: 1 ch) 60 2.7 v m pd780078 48 k to 60 k 2 ch C 8 ch 3 ch (uart: 2 ch) 52 1.8 v m pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 m pd780024a 8 ch C m pd78014h 2 ch 53 m pd78018f 8 k to 60 k m pd78083 8 k to 16 k C C 1 ch (uart: 1 ch) 33 C inverter m pd780988 16 k to 60 k 3 ch note C 1 ch C 8 ch C 3 ch (uart: 2 ch) 47 4.0 v ? control fip m pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C C 2 ch 74 2.7 v C drive m pd780228 48 k to 60 k 3 ch C C 1 ch 72 4.5 v m pd780232 16 k to 24 k 4 ch 2 ch 40 m pd78044h 32 k to 48 k 2 ch 1 ch 1ch 8 ch 1 ch 68 2.7 v m pd78044f 16 k to 40 k 2 ch lcd m pd780308 48 k to 60 k 2 ch 1 ch 1ch 1 ch 8 ch C C 3 ch (time-division 57 2.0 v C drive uart: 1 ch) m pd78064b 32 k 2 ch (uart: 1 ch) m pd78064 16 k to 32 k call id m pd780841 24 k to 32 k 1 ch 1 ch 1 ch 1 ch 2 ch C C 2 ch (uart: 1 ch) 57 2.7 v C bus m pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch C C 3 ch (uart: 1 ch) 79 4.0 v ? interface m pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v C supported m pd780814 32 k to 60 k 2 ch 12 ch C 2 ch (uart: 1 ch) 46 4.0 v meter m pd780958 48 k to 60 k 4 ch 2 ch C 1 ch C C C 2 ch (uart: 1 ch) 69 2.2 v C control m pd780955 40 k 6 ch 1 ch 1 ch 2 ch (uart: 2 ch) 50 m pd780852 32 k to 40 k 3 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v m pd780824 32 k to 60 k 2 ch (uart: 1 ch) 59 4.0 v note 16-bit timer: 2 channels 10-bit timer: 1 channel
5 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 the major functional differences among the y subseries are shown below. function rom capacity configuration of serial interface i/o v dd min. subseries name value control m pd78078y 48 k to 60 k 88 1.8 v m pd780018ay 48 k to 60 k 88 m pd780058y 24 k to 60 k 68 1.8 v m pd78058fy 48 k to 60 k 69 2.7 v m pd780078y 48 k to 60 k 52 1.8 v m pd780034ay 8 k to 32 k 51 1.8 v m pd78018fy 8 k to 60 k 53 lcd m pd780308y 48 k to 60 k 57 2.0 v drive m pd78064y 16 k to 32 k remark the functions other than the serial interface are common to the subseries without y. 3-wire/2-wire/i 2 c : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/uart : 1 ch 3-wire with automatic transmit/receive function : 1 ch time-division 3-wire : 1 ch i 2 c bus (multimaster supported) : 1 ch 3-wire/2-wire/i 2 c : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/time-division uart : 1 ch 3-wire/2-wire/i 2 c : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/uart : 1 ch 3-wire : 1 ch uart : 1 ch 3-wire/uart : 1 ch i 2 c bus (multimaster supported) : 1 ch uart : 1 ch 3-wire : 1 ch i 2 c bus (multimaster supported) : 1 ch 3-wire/2-wire/i 2 c : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/2-wire/i 2 c : 1 ch 3-wire/time-division uart : 1 ch 3-wire : 1 ch 3-wire/2-wire/i 2 c : 1 ch 3-wire/uart : 1 ch m pd78070ay - m pd78054y 16 k to 60 k m pd780024ay 61 2.7 v 2.0 v
6 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 overview of functions when main system clock is selected when subsystem clock is selected item product name m pd78f0058 m pd78f0058y 60 kbytes 1,024 bytes 32 bytes 1,024 bytes 64 kbytes 8 bits 32 registers (8 bits 8 registers 4 banks) 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@5.0 mhz operation) 122 m s (@32.768 khz operation) ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjust, etc. total: 68 ? cmos input: 2 ? cmos i/o: 62 ? n-ch open-drain i/o: 4 ? 8-bit resolution 8 channels (v dd = 2.7 to 5.5 v) ? 8-bit resolution 2 channels (v dd = 2.7 to 5.5 v) ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable: 1 channel ? 3-wire serial i/o mode (automatic data transmit/receive function for up to 32 bytes provided on chip): 1 channel ? 3-wire/serial i/o/uart mode (time division transfer function provided on chip) selectable: 1 channel ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel 3 (14-bit pwm output 1) 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@5.0 mhz operation with main system clock) 32.768 khz (@32.768 khz operation with subsystem clock) 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@5.0 mhz operation with main system clock) internal: 13, external: 6 internal: 1 1 internal: 1, external: 1 v dd = 2.7 to 5.5 v t a = C40 to +85 c ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.0 mm) internal memory flash memory high-speed ram buffer ram expanded ram maskable non-maskable software vectored interrupt sources ? 3-wire serial i/o/2-wire serial i/o/ i 2 c mode selectable: 1 channel memory space general registers minimum instruction execution time instruction set i/o ports a/d converter d/a converter serial interface timers timer outputs clock output buzzer output test inputs supply voltage operating ambient temperature package
7 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 contents 1. pin configuration (top view) ........................................................................................... 8 2. block diagram .......................................................................................................................... 10 3. differences between m pd78f0058, 78f0058y, and mask rom versions ............... 11 3.1 memory size switching register (ims) ................................................................................................ 12 3.2 internal expansion ram size switching register (ixs) .................................................................... 13 4. pin functions ............................................................................................................................. 14 4.1 port pins ............................................................................................................................... .................... 14 4.2 non-port pins ............................................................................................................................... ............ 16 4.3 pin i/o circuits and recommended connection of unused pins .................................................... 18 5. memory space ........................................................................................................................... 22 6. flash memory programming ............................................................................................... 23 6.1 selection of transmission mode ........................................................................................................... 23 6.2 function of flash memory programming ............................................................................................ 24 6.3 connection of flashpro iii ...................................................................................................................... 24 6.4 example of settings for flashpro iii (pg-fp3) .................................................................................... 26 7. electrical specifications .................................................................................................. 27 8. package drawings ................................................................................................................. 56 9. recommended soldering conditions ........................................................................... 59 appendix a. development tools .......................................................................................... 61 appendix b. related documents .......................................................................................... 64
8 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 1. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd78f0058gc-8bt, 78f0058ygc-8bt ? 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.05 mm) m pd78f0058gk-be9, 78f0058ygk-be9 ? 80-pin plastic tqfp (fine pitch) (12 12 mm, resin thickness 1.0 mm) m pd78f0058gk-9eu note , 78f0058ygk-9eu note note under development cautions 1. connect the v pp pin directly to v ss0 or v ss1 in normal operation mode. 2. connect the av ss pin to v ss0 . remarks 1. [ ]: m pd78f0058y only. 2. when the microcontroller is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 reset p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd0 p71/so2/txd0 p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb/txd1 p24/busy/rxd1 p25/si0/sb0 [/sda0] p26/so0/sb1 [/sda1] p27/sck0 [/scl] p40/ad0 p41/ad1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 v dd0 xt1/p07 xt2 v pp x1 x2 v dd1 v ss0 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss1 p56/a14 p57/a15 p60 p61 p62 p63 p64/rd
9 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 a8 to a15 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input ano0, ano1 : analog output asck : asychronous serial clock astb : address strobe av ref0 , av ref1 : analog reference voltage av ss : analog ground busy : busy buz : buzzer clock intp0 to intp5 : interrupt from peripherals p00 to p05, p07 : port 0 p10 to p17 : port 1 p20 to p27 : port 2 p30 to p37 : port 3 p40 to p47 : port 4 p50 to p57 : port 5 p60 to p67 : port 6 p70 to p72 : port 7 p120 to p127 : port 12 p130, p131 : port 13 pcl : programmable clock rd : read strobe reset : reset rtp0 to rtp7 : real-time output port rxd0, rxd1 : receive data sb0, sb1 : serial bus sck0 to sck2 : serial clock scl : serial clock sda0, sda1 : serial data si0 to si2 : serial input so0 to so2 : serial output stb : strobe ti00, ti01 : timer input ti1, ti2 : timer input to0 to to2 : timer output txd0, txd1 : transmit data v dd0 , v dd1 : power supply v pp : programming power supply v ss0 , v ss1 : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) pin identification
10 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 2. block diagram remark [ ]: m pd78f0058y only. 16-bit timer/ event counter watchdog timer to0/p30 ti00/intp0/p00 ti01/intp1/p01 8-bit timer/ event counter 1 to1/p31 ti1/p33 8-bit timer/ event counter 2 to2/p32 ti2/p34 watch timer serial interface 0 si0/sb0 [/sda0] /p25 so0/sb1 [/sda1] /p26 sck0 [/scl] /p27 serial interface 1 si1/p20 so1/p21 sck1/p22 stb/txd1/p23 serial interface 2 a/d converter av ss av ref0 ani0/p10 to ani7/p17 d/a converter av ss av ref1 ano0/p130, ano1/p131 intp0/p00 to intp5/p05 interrupt control buzzer output clock output control buz/p36 pcl/p35 v dd0 , v dd1 v ss0 , v ss1 v pp ram 78k/0 cpu core flash memory port 0 p01 to p05 p00 p07 port 1 p10 to p17 port 2 p20 to p27 port 3 p30 to p37 port 4 p40 to p47 port 5 p50 to p57 port 6 p60 to p67 port 7 p70 to p72 port 12 p120 to p127 port 13 p130, p131 external access ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 real-time output port rtp0/p120 to rtp7/p127 system control reset x1 x2 xt1/p07 xt2 busy/rxd1/p24 stb/txd1/p23 si2/rxd0/p70 so2/txd0/p71 sck2/asck/p72 busy/rxd1/p24
11 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 3. differences between m pd78f0058, 78f0058y, and mask rom versions the m pd78f0058 and 78f0058y are products provided with a flash memory which enables on-board reading, erasing, and rewriting of programs with device mounted on target system. the functions of the m pd78f0058 and 78f0058y (except the functions specified for flash memory and mask option of p60 to p63 pins) can be made the same as those of the mask rom versions by setting the memory size switching register (ims) and internal expansion ram size switching register (ixs). table 3-1 shows the differences between the flash memory version ( m pd78f0058, 78f0058y) and the mask rom versions ( m pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y,780056y, and 780058y). table 3-1. differences between m pd78f0058, 78f0058y and mask rom versions item m pd78f0058 m pd78f0058y mask rom versions m pd780058 m pd780058y subseries subseries internal rom structure flash memory mask rom internal rom capacity 60 kbytes m pd780053, 780053y : 24 kbytes m pd780054, 780054y : 32 kbytes m pd780055, 780055y : 40 kbytes m pd780056, 780056y : 48 kbytes m pd780058, 780058y : 60 kbytes internal expansion ram capacity 1024 bytes m pd780053, 780053y : none m pd780054, 780054y : none m pd780055, 780055y : none m pd780056, 780056y : none m pd780058, 780058y : 1024 bytes internal rom capacity changeable/not changeable note 1 not changeable changeable with memory size switching register (ims) internal expansion ram capacity changeable note 2 not changeable changeable/not changeable with internal expansion ram size switching register (ixs) supply voltage v dd = 2.7 to 5.5 v v dd = 1.8 to 5.5 v ic pin not provided provided v pp pin provided not provided p60 to p63 pin mask option with internal not provided provided pull-up resistors serial interface (sbi) provided not provided provided not provided serial interface (i 2 c) not provided provided not provided provided notes 1. flash memory is set to 60 kbytes by reset input. 2. internal expansion ram is set to 1024 bytes by reset input. caution the noise resistance and noise radiation differ between flash memory versions and mask rom versions. when considering the replacement of flash memory versions with mask rom versions in the process from trial manufacturing to mass production, adequate evaluation should be carried out using cs products (not es products) of mask rom versions. remark only the m pd780058, 780058y, 78f0058, and 78f0058y are provided with ixs.
12 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 3.1 memory size switching register (ims) this register sets a part of internal memory unused by software. the memory mapping can be made the same as that of mask rom versions with different types of internal memory (rom and ram) by setting the memory size switching register (ims). the ims is set with an 8-bit memory manipulation instruction. reset input sets the ims to cfh. figure 3-1. format of memory size switching register note when using external device expansion function, set the internal rom capacity to less than 56 kbytes. table 3-2 shows the ims set value to make the memory mapping the same as those of mask rom versions. table 3-2. set value of memory size switching register target mask rom versions ims set value m pd780053, 780053y c6h m pd780054, 780054y c8h m pd780055, 780055y cah m pd780056, 780056y cch m pd780058, 780058y cfh ram2 7 ram1 6 ram0 5 0 4 rom3 3 rom2 2 rom1 1 rom0 0 ims symbol fff0h address cfh at reset r/w r/w rom3 0 1 1 1 1 1 rom2 1 0 0 1 1 1 rom1 1 0 1 0 1 1 rom0 0 0 0 0 0 1 selection of internal rom capacity 24 kbytes 32 kbytes 40 kbytes 48 kbytes 56 kbytes note 60 kbytes setting prohibited others ram2 1 ram1 1 ram0 0 selection of internal high-speed ram capacity 1024 bytes setting prohibited others
13 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 3.2 internal expansion ram size switching register (ixs) this register sets the internal expansion ram capacity by software. the memory mapping can be made the same as that of mask rom versions with different types of internal expansion ram by setting the internal expansion ram size switching register (ixs). the ixs is set with an 8-bit memory manipulation instruction. reset input sets the ixs to 0ah. figure 3-2. format of internal expansion ram size switching register table 3-3 shows the ixs set value to make the memory mapping the same as those of mask rom versions. table 3-3. set value of internal expansion ram size switching register target mask rom versions ims set value m pd780053, 780053y 0ch m pd780054, 780054y m pd780055, 780055y m pd780056, 780056y m pd780058, 780058y 0ah 0 7 0 6 0 5 0 4 ixram3 3 ixram2 2 ixram1 1 ixram0 0 ixs symbol fff4h address 0ah at reset w r/w ixram3 1 1 ixram2 1 0 ixram1 0 1 ixram0 0 0 selection of internal expansion ram capacity 0 bytes 1024 bytes setting prohibited others
14 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 alternate function pin name i/o input only input input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. i/o input only port 1 8-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software note 2 . i/o i/o port 2 8-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 3 8-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. i/o i/o port 4 8-bit input/output port input/output can be specified in 8-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. the test input flag (krif) is set to 1 by falling edge detection. 4. pin functions 4.1 port pins (1/2) intp0/ti00 intp1/ti01 intp2 intp3 intp4 intp5 xt1 ani0 to ani7 si1 so1 sck1 stb/txd1 busy/rxd1 si0/sb0 [/sda0] so0/sb1 [/sda1] sck0 [/scl] to0 to1 to2 ti1 ti2 pcl buz C ad0 to ad7 p00 p01 p02 p03 p04 p05 p07 note 1 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 input function port 0 7-bit input/output port input input after reset input input input input notes 1. when using the p07/xt1 pins as an input port, set bit 6 (frc) of the processor clock control register (pcc) to 1. do not use the on-chip feedback resistor of the subsystem clock oscillator. 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input pins, set port 1 to the input mode. at this time, on-chip pull-up resistors are automatically disconnected. remark [ ]: m pd78f0058y only. input
15 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 p50 to p57 p60 p61 p62 p63 p64 p65 p66 p67 p70 p71 p72 p120 to p127 p130, p131 4.1 port pins (2/2) alternate function function pin name i/o i/o i/o when used as an input port, an on-chip pull-up resistor can be specified by means of software. i/o i/o i/o n-ch open-drain input/output port leds can be driven directly. after reset port 5 8-bit input/output port leds can be driven directly. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 6 8-bit input/outport port input/output can be specified in 1-bit units. port 13 2-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 12 8-bit input/output port input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistor can be specified by means of software. port 7 3-bit input/output port input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. input input input input input a8 to a15 C rd wr wait astb si2/rxd0 so2/txd0 sck2/asck rtp0 to rtp7 ano0, ano1
16 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 alternate function function pin name i/o input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising edge and falling edges) can be specified. input serial interface serial data input output serial interface serial data output serial interface serial data input/output i/o i/o serial interface serial clock input/output input output input input output serial interface automatic transmit/receive busy input 4.2 non-port pins (1/2) p00/ti00 p01/ti01 p02 p03 p04 p05 p25/sb0 [/sda0] p20 p70/rxd p26/sb1 [/sda1] p21 p71/txd p25/si0 [/sda0] p26/so0 [/sda1] p25/si0/sb0 p26/so0/sb1 p27 [/scl] p22 p72/asck p27/sck0 p23/txd1 p24/rxd1 p70/si2 p24/busy p71/so2 p23/stb p72/sck2 p00/intp0 p01/intp1 p33 p34 p30 p31 p32 p35 p36 p120 to p127 p40 to p47 input intp0 intp1 intp2 intp3 intp4 intp5 si0 si1 si2 so0 so1 so2 sb0 sb1 sda0 sda1 sck0 sck1 sck2 scl stb busy rxd0 rxd1 txd0 txd1 asck ti00 ti01 ti1 ti2 to0 to1 to2 pcl buz rtp0 to rtp7 ad0 to ad7 output 16-bit timer (tm0) output (also used for 14-bit pwm output) 8-bit timer (tm1) output 8-bit timer (tm2) output clock output (for trimming of main system clock and subsystem clock) buzzer output real-time output port from which data is output in synchronization with a trigger lower address/data bus for expanding memory externally output output output after reset input input input input input input input input input input input input input asynchronous serial interface serial data output asynchronous serial interface serial data input asynchronous serial interface serial clock input external count clock input to the 16-bit timer (tm0) capture trigger signal input to the capture register (cr00) external count clock input to the 8-bit timer (tm1) external count clock input to the 8-bit timer (tm2) m pd78f0058y only m pd78f0058y only i/o serial interface automatic transmit/receive strobe output input input input remark [ ]: m pd78f0058y only.
17 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 4.2 non-port pins (2/2) alternate function function pin name i/o p50 to p57 p64 p65 after reset input input input output input output input input C input input C input C C C C C C wait astb ani0 to ani7 ano0, ano1 av ref0 av ref1 av ss reset x1 x2 xt1 xt2 v dd0 v ss0 v dd1 v ss1 v pp wait insertion at external memory access strobe output that externally latches address information output to ports 4 and 5 to access external memory. a/d converter analog input d/a converter analog output a/d converter reference voltage input (also used for analog power supply) d/a converter reference voltage input a/d converter and d/a converter ground potential use at the same potential as v ss0 . system reset input connecting crystal resonator for main system clock oscillation connecting crystal resonator for subsystem clock oscillation port block positive power supply port block ground potential positive power supply (except for port and analog blocks) ground potential (except for port and analog blocks) setting flash memory programming mode. applying high voltage for program write/verify. connect directly to v ss0 or v ss1 in normal operation mode. p66 p67 p10 to p17 p130, p131 C C C C C C p07 C C C C C C input input input input input a8 to a15 rd wr output output higher address bus for expanding memory externally strobe signal output for reading from external memory strobe signal output for writing to external memory C C C C C C C C C C C C
18 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 4.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 4-1. for the input/output circuit configuration of each type, see figure 4-1. table 4-1. input/output circuit type of each pin (1/2) input/output circuit type 2 8-c 16 11-d 8-c 5-h 8-c 5-h 8-c 10-b 5-h 8-c 5-h 5-n 5-h 13-k 5-h input i/o input i/o connect to v ss0 . input : independently connect to v ss0 via a resistor. output : leave open. connect to v dd0 . p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p07/xt1 p10/ani0 to p17/ani7 p20/si1 p21/so1 p22/sck1 p23/stb/txd1 p24/busy/rxd1 p25/si0/sb0 [/sda0] p26/so0/sb1 [/sda1] p27/sck0 [/scl] p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60 to p63 p64/rd p65/wr p66/wait p67/astb pin name i/o recommended connection input : independently connect to v dd0 or v ss0 via a resistor. output : leave open. input : independently connect to v dd0 via a resistor. output : leave open. input : independently connect to v dd0 or v ss0 via a resistor. output : leave open. input : independently connect to v dd0 via a resistor. output : leave open. input : independently connect to v dd0 or v ss0 via a resistor. output : leave open. remark [ ]: m pd78f0058y only.
19 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 table 4-1. input/output circuit type of each pin (2/2) input/output circuit type p70/si2/rxd0 p71/so2/txd0 p72/sck2/asck p120/rtp0 to p127/rtp7 p130/ano0, p131/ano1 reset xt2 av ref0 av ref1 av ss v pp pin name i/o recommended connection 8-c 5-h 8-c 5-h 12-c 2 16 C i/o input C input : independently connect to v ss0 via a resistor. output : leave open. C leave open. connect to v ss0 . connect to v dd0 . connect to v ss0 . connect directly to v ss0 or v ss1 . input : independently connect to v dd0 or v ss0 via a resistor. output : leave open.
20 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 figure 4-1. pin input/output circuits (1/2) type 2 in type 8-c pullup enable data output disable v dd0 p-ch v n-ch p-ch in/out ss0 v ss0 v ss0 v ss0 v ss0 v ss0 v dd0 type 10-b enable type 11-d pullup enable data output disable v dd0 p-ch n-ch p-ch in/out v dd0 type 5-h input enable type 5-n pullup enable data output disable v dd0 p-ch n-ch p-ch in/out v dd0 schmitt-triggered input with hysteresis characteristic pullup enable data output disable in/out n-ch v ref input (threshold voltage) v dd0 p-ch n-ch p-ch v dd0 p-ch + - comparator pullup enable data output disable v p-ch n-ch p-ch in/out dd0 v dd0 open drain
21 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 figure 4-1. pin input/output circuits (2/2) type 12-c type 16 pullup enable data output disable v dd0 p-ch n-ch p-ch in/out v ss0 v ss0 v ss0 v dd0 n-ch input enable type 13-k data output disable n-ch p-ch in/out v dd0 rd middle-voltage input buffer p-ch analog output voltage xt1 feedback cut-off xt2 p-ch
22 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 5. memory space figure 5-1 shows the memory map of the m pd78f0058 and 78f0058y. figure 5-1. memory map note the area between f000h and f3ffh cannot be used when the flash memory size is 60 kbytes. this area can be used by setting the flash memory size to 56 kbytes or less with the memory size switching register (ims). special function register (sfr) 256 8 bits internal high-speed ram 1024 8 bits general registers 32 8 bits internal buffer ram 32 8 bits use prohibited use prohibited internal expansion ram 1024 8 bits flash memory 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area use prohibited note ffffh ff00h feffh fb00h faffh fac0h fabfh 1000h 0fffh 0800h 07ffh 0040h 003fh 0080h 007fh 0000h efffh f800h f7ffh fae0h fadfh f400h f3ffh 0000h f000h efffh fee0h fedfh
23 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 6. flash memory programming the program memory provided in the m pd78f0058 and 78f0058y is flash memory. writing to a flash memory can be performed without removing the memory from the target system (on-board). writing is performed connecting the dedicated flash programmer (flashpro iii (part number : fl-pr3, pg-fp3) to the host machine and the target system. remark fl-pr3 is a product of naito densei machida mfg. co., ltd. 6.1 selection of transmission mode writing to a flash memory is performed using the flashpro iii with a serial transmission mode. one of the transmission mode is selected from those in table 6-1. the selection of the transmission mode is made by using the format shown in figure 6-1. each transmission mode is selected by the number of v pp pulses shown in table 6-1. table 6-1. list of transmission mode transmission mode channels pin v pp pulses 3-wire serial i/o 3 p27/sck0 [/scl] 0 p26/so0/sb1 [/sda1] p25/si0/sb0 [/sda0] p22/sck1 1 p21/so1 p20/si1 p72/sck2/asck 2 p71/so2/txd0 p70/si1/rxd0 uart 2 p71/so2/txd0 8 p70/si2/rxd0 p23/txd1 9 p24/rxd1 pseudo 3-wire serial i/o note 1 p32/to2 (serial clock input/output) 12 p31/to1 (serial data output) p30/to0 (serial data input) note serial transmission is performed by controlling the port using software. caution select a communication mode always using the number of v pp pulses shown in table 6-1. remark [ ] : m pd78f0058y only.
24 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 figure 6-1. format of transmission mode selection 6.2 function of flash memory programming operations such as writing to a flash memory are performed by various command/data transmission and reception operations according to the selected transmission mode. table 6-2 shows major functions of flash memory programming. table 6-2. major functions of flash memory programming functions descriptions batch delete batch blank check data write batch verify deletes the entire memory contents. checks the deletion status of the entire memory. performs write to the flash memory based on the write start address and the number of data to be written (number of bytes). compares the entire memory contents with the input data. 10 v v dd v pp 12 n reset v dd v ss v ss 6.3 connection of flashpro iii the connection of the flashpro iii and the m pd78f0058 and 78f0058y differs according to the transmission mode (3-wire serial i/o, uart, pseudo 3-wire). the connection for each transmission mode is shown in figures 6-2 to 6-4. figure 6-2. connection of flashpro iii for 3-wire serial i/o mode v pp n note v dd reset sck so si gnd v pp v dd0 , v dd1 reset sck0, sck1, sck2 clk x1 si0, si1, si2 so0, so1, so2 v ss0 , v ss1 note n = 1, 2 flashpro iii pd78f0058, 78f0058y m
25 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 figure 6-3. connection of flashpro iii for uart mode figure 6-4. connection of flashpro iii for pseudo 3-wire serial i/o mode v pp n note v dd reset so si gnd v pp v dd0 , v dd1 reset rxd0, rxd1 clk x1 txd0, txd1 v ss0 , v ss1 flashpro iii pd78f0058, 78f0058y m note n = 1, 2 v pp n note v dd reset sck so si gnd v pp v dd0 , v dd1 reset p32 (serial clock) clk x1 p30 (serial input) p31(serial output) v ss0 , v ss1 flashpro iii pd78f0058, 78f0058y m note n = 1, 2
26 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 6.4 example of settings for flashpro iii (pg-fp3) make the following setting when writing to flash memory using flashpro iii (pg-fp3) <1> load the parameter file. <2> select serial mode and serial clock using the type command. <3> an example of the settings for the pg-fp3 is shown below. table 6-3. example of settings for pg-fp3 communication mode example of setting for pg-fp3 number of v pp pulses note 1 3-wire serial i/o comm port sio-ch0/1/2 0/1/2 cpu clk on target board in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz sio clk 1.0 mhz uart comm port uart-ch0/1 8/9 cpu clk on target board on target board 4.1943 mhz uart bps 9600 bps note 2 pseudo 3-wire comm port porta 12 cpu clk on target board in flashpro on target board 4.1943 mhz sio clk 1.0 khz in flashpro 4.0 mhz sio clk 1.0 khz notes 1. the number of v pp pulses supplied from flashpro iii when serial communication is initialized. the pins to be used for communication are determined according to the number of these pulses. 2. select one of 9600 bps, 19200 bps, 38400 bps, or 768000 bps. remark comm port : selection of serial port sio clk : selection of serial clock frequency cpu clk : selection of source of cpu clock to be input
27 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 7. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +6.5 v v pp C0.3 to +10.5 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00-p05, p07, p10-p17, p20-p27, p30-p37, p40-p47, C0.3 to v dd + 0.3 v p50-p57, p64-p67, p70-p72, p120-p127, p130, p131, x1, x2, xt2, reset v i2 p60-p63 n-ch open drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10-p17 analog input pin av ss C 0.3 to av ref0 + 0.3 v output i oh per pin C10 ma current, high total for p01-p05, p30-p37, p56, p57, p60-p67, C15 ma p120-p127 total for p10-p17, p20-p27, p40-p47, p50-p55, C15 ma p70-p72, p130, p131 output i ol note per pin peak value 30 ma current, low rms value 15 ma total for p50-p55 peak value 100 ma rms value 70 ma total for p56, p57, p60-p63 peak value 100 ma rms value 70 ma total for p10-p17, p20-p27, peak value 50 ma p40-p47, p70-p72, p130, p131 rms value 20 ma total for p01-p05, p30-p37, peak value 50 ma p64-p67, p120-p127 rms value 20 ma operating ambient t a during normal operation C40 to +85 c temperature during flash memory programming 10 to 40 c storage t stg C65 to +125 c temperature note the rms value should be calculated as follows: [rms value] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
28 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) recommended circuit typ. max. 5.0 4 5.0 10 30 5.0 500 unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock parameter oscillation frequency (f x ) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high-/low-level width (t xh , t xl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss1 . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. min. 1.0 1.0 conditions v dd = oscillation voltage range after v dd reaches oscillation voltage range min. x1 x2 pd74hcu04 m 1.0 85 v dd = 4.5 to 5.5 v x1 v pp x2 c1 c2 x1 v pp x2 c1 c2
29 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p01-p05, p10-p17, 15 pf capacitance unmeasured pins returned p20-p27, p30-p37, to 0 v. p40-p47, p50-p57, p64-p67, p70-p72, p120-p127, p130, p131 p60-p63 20 pf remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) min. 32 32 5 notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions v dd = 4.5 to 5.5 v typ. 32.768 1.2 max. 35 2 10 100 15 unit khz s khz m s cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss1 . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. recommended circuit parameter symbol conditions min. typ. max. unit capacitance (t a = 25 c , v dd = v ss = 0 v) xt1 xt2 pd74hcu04 m xt1 v pp xt2 c4 c3 r2 remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
30 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10-p17, p21, p23, p30-p32, v dd = 2.7 to 5.5 v 0.7v dd v dd v high p35-p37, p40-p47, p50-p57, p64-p67, p71, p120-p127, p130, p131 v ih2 p00-p05, p20, p22, p24-p27, v dd = 2.7 to 5.5 v 0.8v dd v dd v p33, p34, p70, p72, reset v ih3 p60-p63 v dd = 2.7 to 5.5 v 0.7v dd 15 v (n-ch open drain) v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 5.5 v 0.8v dd v dd v 2.7 v v dd < 4.5 v 0.9v dd v dd v input voltage, v il1 p10-p17, p21, p23, p30-p32, v dd = 2.7 to 5.5 v 0 0.3v dd v low p35-p37, p40-p47, p50-p57, p64-p67, p71, p120-p127, p130, p131 v il2 p00-p05, p20, p22, p24-p27, v dd = 2.7 to 5.5 v 0 0.2v dd v p33, p34, p70, p72, reset v il3 p60-p63 4.5 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.5 v 0 0.2v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v v il5 xt1/p07, xt2 4.5 v v dd 5.5 v 0 0.2v dd v 2.7 v v dd < 4.5 v 0 0.1v dd v output voltage, v oh v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v high i oh = C100 m av dd C 0.5 v output voltage, v ol1 p50-p57, p60-p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v low i ol = 15 ma p01-p05, p10-p17, p20-p27, v dd = 4.5 to 5.5 v, 0.4 v p30-p37, p40-p47, p64-p67, i ol = 1.6 ma p70-p72, p120-p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2v dd v open drain, pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
31 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00-p05, p10-p17, p20-p27, 3 m a current, high p30-p37, p40-p47, p50-p57, p60-p67, p70-p72, p120-p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a input leakage i lil1 v in = 0 v p00-p05, p10-p17, p20-p27, C3 m a current, low p30-p37, p40-p47, p50-p57, p64-p67, p70-p72, p120-p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60-p63 C3 note 1 m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low software pull-up r v in = 0 v, p01-p05, p10-p17, p20-p27, p30-p37, 15 30 90 k w resistor note 2 p40-p47, p50-p57, p64-p67, p70-p72, p120-p127, p130, p131 notes 1. a low-level input leakage current of C200 m a (max.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (p6) or port mode register 6 (pm6). at times other than this 1.5- clock interval, a C3 m a (max.) current flows. 2. software pull-up resistor can only be used within the range v dd = 2.7 to 5.5 v. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
32 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 v dd = 5.0 v 10% note 1 6.2 12.5 ma v dd = 3.0 v 10% note 2 1.3 3.1 ma v dd = 5.0 v 10% note 1 13.1 25.7 ma v dd = 3.0 v 10% note 2 2.1 4.9 ma v dd = 5.0 v 10% peripheral functions 5.6 ma operating peripheral functions 1.0 2.8 ma not operating v dd = 3.0 v 10% peripheral functions 2.9 ma operating peripheral functions 0.44 1.1 ma not operating v dd = 5.0 v 10% peripheral functions 8.4 ma operating peripheral functions 1.3 3.1 ma not operating v dd = 3.0 v 10% peripheral functions 4.5 ma operating peripheral functions 0.6 1.5 ma not operating v dd = 5.0 v 10% 110 220 m a v dd = 3.0 v 10% 86 172 m a v dd = 5.0 v 10% 22.5 45 m a v dd = 3.0 v 10% 3.2 6.4 m a v dd = 5.0 v 10% 1.0 30 m a v dd = 3.0 v 10% 0.5 10 m a v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) i dd1 note 5 5.0 mhz crystal oscillation operating mode (f xx = 5.0 mhz) note 4 5.0 mhz crystal oscillation halt mode (f xx = 5.0 mhz) note 4 i dd2 5.0 mhz crystal oscillation halt mode (f xx = 2.5 mhz) note 3 i dd3 note 5 32.768 khz crystal oscillation operating mode note 6 i dd4 note 5 32.768 khz crystal oscillation halt mode note 6 i dd5 note 5 i dd6 note 5 xt1 = v dd stop mode when feedback resistor is not used parameter symbol conditions min. typ. max. unit power supply current note 5 5.0 mhz crystal oscillation operating mode (f xx = 2.5 mhz) note 3 notes 1. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 2. low-speed mode operation (when pcc is set to 04h). 3. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is set to 00h) 4. operation with main system clock f xx = f x (when osms is set to 01h) 5. refers to the current flowing to the v dd0 and v dd1 pins. the current flowing to the a/d converter, d/a converter, and on-chip pull-up resistor is not included. 6. when the main system clock operation is stopped. xt1 = v dd stop mode when feedback resistor is used
33 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with main system v dd = 2.7 to 5.5 v 0.8 64 m s (min. instruction clock (f xx = 2.5 mhz) note 1 execution time) operating with main system 3.5 v v dd 5.5 v 0.4 32 m s clock (f xx = 5.0 mhz) note 2 2.7 v v dd < 3.5 v 0.8 32 m s operating with subsystem clock 40 note 3 122 125 m s ti00 input high-/ t tih00 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 m s low-level width t til00 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 m s ti01 input high-/ t tih01 v dd = 2.7 to 5.5 v 10 m s low-level width t til01 ti1, ti2 input f ti1 v dd = 4.5 to 5.5 v 0 4 mhz frequency 0 275 khz ti1, ti2 input t tih1 v dd = 4.5 to 5.5 v 100 ns high-/low-level t til1 1.8 m s width interrupt request t inth intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 m s input high-/ t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 m s low-level width intp1-intp5, p40-p47 v dd = 2.7 to 5.5 v 10 m s reset low- t rsl v dd = 2.7 to 5.5 v 10 m s level width notes 1. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is set to 00h) 2. operation with main system clock f xx = f x (when osms is set to 01h) 3. value when external clock is used. when a crystal resonator is used, it is 114 m s (min.) 4. selection of f sam = f xx /2 n , f xx /32, f xx /64, and f xx /128 is possible with bits 0 and 1 (scs0, scs1) of the sampling clock select register (scs) (when n= 0 to 4).
34 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 t cy vs. v dd (@ f xx = f x main system clock operation) t cy vs. v dd (@ f xx = f x /2 main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] guaranteed operation range 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] guaranteed operation range cycle time t cy [ s] m cycle time t cy [ s] m
35 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (2) read/write operation parameter symbol conditions min. max. unit astb high-level width t asth 0.85t cy C 50 ns address setup time t ads 0.85t cy C 50 ns address hold time t adh 50 ns data input time from address t add1 (2.85 + 2n)t cy C 80 ns t add2 (4 + 2n)t cy C 100 ns data input time from rd t rdd1 (2 + 2n)t cy C 100 ns t rdd2 (2.85 + 2n)t cy C 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy C 60 ns t rdl2 (2.85 + 2n)t cy C 60 ns wait input time from rd t rdwt1 0.85t cy C 50 ns t rdwt2 2t cy C 60 ns wait input time from wr t wrwt 2t cy C 60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy C 100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85 + 2n)t cy C 60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy + 20 ns astb - delay time from t rdast 0.85t cy C 10 1.15t cy + 20 ns rd - at external fetch address hold time from t rdadh 0.85t cy C 50 1.15t cy + 50 ns rd - at external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 050ns address hold time from wr - t wradh 0.85t cy 1.15t cy + 40 ns rd - delay time from wait - t wtrd 1.15t cy + 40 3.15t cy + 40 ns wr - delay time from wait - t wtwr 1.15t cy + 30 3.15t cy + 30 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to +85 c, v dd = 3.5 to 5.5 v)
36 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (b) when mcs = 0 or pcc2 to pcc0 1 000b (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth t cy C 80 ns address setup time t ads t cy C 80 ns address hold time t adh 0.4t cy C 10 ns data input time from address t add1 (3 + 2n)t cy C 160 ns t add2 (4 + 2n)t cy C 200 ns data input time from rd t rdd1 (1.4 + 2n)t cy C 70 ns t rdd2 (2.4 + 2n)t cy C 70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n)t cy C 20 ns t rdl2 (2.4 + 2n)t cy C 20 ns wait input time from rd t rdwt1 t cy C 100 ns t rdwt2 2t cy C 100 ns wait input time from wr t wrwt 2t cy C 100 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.4 + 2n)t cy C 60 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.4 + 2n)t cy C 20 ns rd delay time from astb t astrd 0.4t cy C 30 ns wr delay time from astb t astwr 1.4t cy C 30 ns astb - delay time from rd - t rdast t cy C 10 t cy + 20 ns at external fetch address hold time from t rdadh t cy C 50 t cy + 50 ns rd - at external fetch write data output time from t rdwd 0.4t cy C 20 ns rd - write data output time from t wrwd 060ns wr address hold time from wr - t wradh t cy t cy + 60 ns rd - delay time from wait - t wtrd 0.6t cy + 180 2.6t cy + 180 ns wr - delay time from wait - t wtwr 0.6t cy + 120 2.6t cy + 120 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
37 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (3) serial interface (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns t kh1 , t kl1 v dd = 4.5 to 5.5 v t kcy1 /2 C 50 ns t kcy1 /2 C 100 ns t sik1 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of the sck0 and so0 output lines. parameter symbol conditions min. typ. max. unit t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns t kh2 , t kl2 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns t sik2 2.7 v v dd 5.5 v 100 ns t ksi2 400 ns t kso2 c = 100 pf note 300 ns t r2 , t f2 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 - ) si0 hold time (from sck0 - ) so0 output delay time from sck0 sck0 rise/fall time (ii) 3-wire serial i/o mode (sck0... external clock input) note c is the load capacitance of the so0 output line. sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 - ) si0 hold time (from sck0 - ) so0 output delay time from sck0
38 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (iv) 2-wire serial i/o mode (sck0... external clock input) parameter symbol conditions min. typ. max. unit t kcy4 2.7 v v dd 5.5 v 1,600 ns t kh4 2.7 v v dd 5.5 v 650 ns t kl4 2.7 v v dd 5.5 v 800 ns t sik4 v dd = 2.7 to 5.5 v 100 ns t ksi4 t kcy4 /2 ns t kso4 4.5 v v dd 5.5 v 0 300 ns 2.7 v v dd < 4.5 v 0 500 ns t r4 , t f4 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function r = 1 k w , c = 100 pf note (iii) 2-wire serial i/o mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 r = 1 k w , 2.7 v v dd 5.5 v 1,600 ns sck0 high-level width t kh3 c = 100 pf note v dd = 2.7 to 5.5 v t kcy3 /2 C 160 ns sck0 low-level width t kl3 v dd = 4.5 to 5.5 v t kcy3 /2 C 50 ns t kcy3 /2 C 100 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 300 ns (to sck0 - ) sb0, sb1 hold time t ksi3 600 ns (from sck0 - ) sb0, sb1 output delay t kso3 0 300 ns time from sck0 note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sck0 rise/fall time 2.7 v v dd < 4.5 v 350 ns
39 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (v) sbi mode (sck0... internal clock output) ( m pd78f0058 only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 3,200 ns sck0 high-/low-level t kh5 , t kl5 4.5 v v dd 5.5 v t kcy5 /2 C 50 ns width 2.7 v v dd < 4.5 v t kcy5 /2 C 150 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.7 v v dd < 4.5 v 300 ns sb0, sb1 hold time t ksi5 t kcy5 /2 ns (from sck0 - ) sb0, sb1 output delay t kso5 r = 1 k w , v dd = 4.5 to 5.5 v 0 250 ns time from sck0 c = 100 pf note 0 1,000 ns sb0, sb1 from sck0 - t ksb t kcy5 ns sck0 from sb0, sb1 t sbk t kcy5 ns sb0, sb1 high-level width t sbh t kcy5 ns sb0, sb1 low-level width t sbl t kcy5 ns note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (vi) sbi mode (sck0... external clock input) ( m pd78f0058 only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 3,200 ns sck0 high-/low-level t kh6 , t kl6 4.5 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.5 v 1,600 ns sb0, sb1 setup time t sik6 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.7 v v dd < 4.5 v 300 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 - ) sb0, sb1 output delay t kso6 r = 1 k w , v dd = 4.5 to 5.5 v 0 300 ns time from sck0 c = 100 pf note 0 1,000 ns sb0, sb1 from sck0 - t ksb t kcy6 ns sck0 from sb0, sb1 t sbk t kcy6 ns sb0, sb1 high-level width t sbh t kcy6 ns sb0, sb1 low-level width t sbl t kcy6 ns sck0 rise/fall time t r6 , t f6 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
40 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (viii) i 2 c bus mode (scl... external clock input) ( m pd78f0058y only) (vii) i 2 c bus mode (scl... internal clock output) ( m pd78f0058y only) note r and c are the load resistance and load capacitance of the scl, sda0, and sda1 output lines. note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines. parameter symbol conditions min. typ. max. unit scl cycle time t kcy7 2.7 v v dd < 5.5 v 10 m s scl high-level width t kh7 2.7 v v dd < 5.5 v t kcy7 C 160 m s scl low-level width t kl7 4.5 v v dd < 5.5 v t kcy7 C 50 ns 2.7 v v dd < 4.5 v t kcy7 C 100 ns sda0, sda1 setup time t sik7 2.7 v v dd < 5.5 v 200 ns (to scl - ) sda0, sda1 hold time t ksi7 0ns (from scl ) sda0, sda1 output delay t kso7 4.5 v v dd < 5.5 v 0 300 ns time from scl 0 500 ns sda0, sda1 from scl - t ksb 200 ns or sda0, sda1 - from scl - scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns r = 1 k w , c = 100 pf note parameter symbol conditions min. typ. max. unit scl cycle time t kcy8 1 m s scl high-level width t kh8 400 ns sda0, sda1 setup time t sik8 200 ns (to scl - ) sda0, sda1 hold time t ksi8 0ns (from scl ) sda0, sda1 output delay t kso8 4.5 v v dd < 5.5 v 0 300 ns time from scl sda0, sda1 from scl - t ksb 200 ns or sda0, sda1 - from scl - scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns r = 1 k w , c = 100 pf note 0ns 500
41 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1...internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck1 high-/low-level width t kh9 , t kl9 v dd = 4.5 to 5.5 v t kcy9 /2 C 50 ns t kcy9 /2 C 100 ns si1 setup time (to sck1 - )t sik9 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns si1 hold time (from sck1 - )t ksi9 400 ns so1 output delay time from sck1 t kso9 c = 100 pf note 300 ns (ii) 3-wire serial i/o mode (sck1...external clock input) note c is the load capacitance of the sck1 and so1 output lines. parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck1 high-/low-level width t kh10 , t kl10 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns si1 setup time (to sck1 - )t sik10 v dd = 2.7 to 5.5 v 100 ns si1 hold time (from sck1 - )t kis10 400 ns so1 output delay time from sck1 t kso10 c = 100 pf note v dd = 2.7 to 5.5 v 300 ns sck1 rise/fall time t r10 , t f10 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line.
42 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1...internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck1 high-/low-level width t kh11 , t kl11 v dd = 4.5 to 5.5 v t kcy11 /2 C 50 ns t kcy11 /2 C 100 ns si1 setup time (to sck1 - )t sik11 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns si1 hold time (from sck1 - )t ksi11 400 ns so1 output delay time from sck1 t kso11 c = 100 pf note 300 ns stb - from sck1 - t sbd t kcy11 /2 C 100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw 2.7 v v dd < 5.5 v t kcy11 C 30 t kcy11 + 30 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal detection timing) 2.7 v v dd < 4.5 v 150 ns sck1 from busy inactive t sps 2t kcy11 ns note c is the load capacitance of the sck1 and so1 output lines. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1...external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck1 high-/low-level width t kh12 , 4.5 v v dd 5.5 v 400 ns t kl12 2.7 v v dd < 4.5 v 800 ns si1 setup time (to sck1 - )t sik12 v dd = 2.7 to 5.5 v 100 ns si1 hold time (from sck1 - )t ksi12 400 ns so1 output delay time from sck1 t kso12 c = 100 pf note v dd = 2.7 to 5.5 v 300 ns sck1 rise/fall time t r12 , t f12 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line.
43 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2...internal clock output) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy13 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck2 high-/low-level width t kh13 ,v dd = 4.5 to 5.5 v t kcy13 /2 C 50 ns t kl13 t kcy13 /2 C 100 ns si2 setup time (to sck2 - )t sik13 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns si2 hold time (from sck2 - )t ksi13 400 ns so2 output delay time from sck2 t kso13 c = 100 pf note 300 ns note c is the load capacitance of the so2 output line. (ii) 3-wire serial i/o mode (sck2...external clock input) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy14 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck2 high-/low-level width t kh14, 4.5 v v dd 5.5 v 400 ns t kl14 2.7 v v dd < 4.5 v 800 ns si2 setup time (to sck2 - )t sik14 v dd = 2.7 to 5.5 v 100 ns si2 hold time (from sck2 - )t ksi14 400 ns so2 output delay time from sck2 t kso14 c = 100 pf note v dd = 2.7 to 5.5 v 300 ns sck2 rise/fall time t r14 , other than below 160 ns t f14 v dd = 4.5 to 5.5 v 1 m s when not using external device expansion function note c is the load capacitance of the so2 output line.
44 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78,125 bps 2.7 v v dd < 4.5 v 39,063 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck cycle time t kcy15 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns asck high-/low-level width t kh15 , t kl15 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns transfer rate 4.5 v v dd 5.5 v 39,063 bps 2.7 v v dd < 4.5 v 19,531 bps asck rise/fall time t r15 , t f15 v dd = 4.5 to 5.5 v, 1,000 ns when not using external device expansion function. 160 ns
45 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y ac timing measurement points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input 1/f ti1 t til1 t tih1 ti1, ti2 t til00 , t til01 t tih00 , t tih01 ti00, ti01 0.8v dd 0.2v dd 0.8v dd 0.2v dd point of measurement
46 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 interrupt request input timing reset input timing t intl t inth intp0 to intp5 t rsl reset
47 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y read/write operation external fetch (no wait): external fetch (wait insertion): t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address operation code t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 higher 8-bit address operation code lower 8-bit address
48 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 external data access (no wait): external data access (wait insertion): t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwd lower 8-bit address t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd lower 8-bit address
49 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y 3-wire serial i/o mode: serial transfer timing t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 t sikm t ksim t ksom input data output data t rn t fn 2-wire serial i/o mode: t kso3, 4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksi3, 4 sb0, sb1 t f4 t r4
50 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y sbi mode (bus release signal transfer): sbi mode (command signal transfer): t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t sbl t sbh t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 t sik5, 6 t kcy5,6 t kl5, 6 t kh5, 6 sck0 t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 i 2 c bus mode : scl sda0, sda1 t klm t sbh m = 7, 8 t sikm t ksb t ksb t khm t kcym t sikm t ksom t sbk t ksim
51 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing) : note the signal is not actually driven low here; it is shown as such to indicate the timing. t bys sck1 t sps busy (active high) 789 note 10 note 10 + n note 1 t byh t sbw t sbd t kcy11, 12 t kh11, 12 t ksi11, 12 t sik11, 12 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r12 t kl11, 12 t f12 t kso11, 12 uart mode (external clock input): t kcy15 t kh15 t kl15 t f15 t r15 asck
52 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y a/d converter characteristics (t a = e40 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 1 2.7 v av ref0 < 4.5 v 1.0 % 4.5 v av ref0 < 5.5 v 0.6 % conversion time t conv 2.7 v av ref0 < 5.5 v 16 100 m s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 v dd v av ref0 current i ref0 when a/d converter is operating note 2 500 1,500 m a when a/d converter is not operating note 3 03 m a parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m w note 1 1.2 % r = 4 m w note 1 0.8 % r = 10 m w note 1 0.6 % settling time c = 30 pf note 1 15 m s output resistance r o note 2 8k w analog reference voltage av ref1 1.8 v dd v av ref1 current i ref1 note 2 2.5 ma resistance between av ref1 and av ss r airef1 dacs0, dacs1 = 55h note 2 48 k w notes 1. excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value. 2. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 1. 3. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 0. d/a converter characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0 and dacs1: d/a conversion value setting registers 0, 1
53 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y data memory stop mode low supply voltage data retention characteristics (t a = e40 to +85 c) note selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). parameter symbol conditions min. typ. max. unit data retention power v dddr 1.8 5.5 v supply voltage data retention power i dddr v dddr = 1.8 v 0.1 10 m a supply current subsystem clock stop and feed-back resistor disconnected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr
54 data sheet u12092ej1v0ds00 m pd78f0058, 78f0058y flash memory programming characteristics (v dd = 2.7 to 5.5 v, t a = 10 to 40 c) (1) write/delete characteristics parameter symbol conditions min. typ. max. unit write current (v dd pin) note 1 t ddw when v pp = v pp1 5.0 mhz crystal oscillation 15.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 28.7 ma operation mode (f xx = 5.0 mhz) note 3 write current (v pp pin) note 1 i ppw when v pp = v pp1 5.0 mhz crystal oscillation 19.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 32.7 ma operation mode (f xx = 5.0 mhz) note 3 delete current (v dd pin) note 1 i dde when v pp = v pp1 5.0 mhz crystal oscillation 15.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 28.7 ma operation mode (f xx = 5.0 mhz) note 3 delete current (v pp pin) note 1 i ppe when v pp = v pp1 100 ma unit delete time t er 0.5 1 1 s total delete time t era 20 s number of overwrite c wrt delete and write are counted as one cycle 20 times v pp power supply voltage v pp0 in normal mode 0 0.2 v dd v v pp1 at flash memory programming 9.7 10.0 10.3 v notes 1. 1. av ref current and port current (current flowing to internal pull-up resistor) are not included. 2. when main system clock is operating at f xx = f xx /2 (when oscillation mode selection resistor (osms) is set to 00h). 3. when main system clock is operating at f xx = f xx (when osms is set to 01h). 2) serial write operation characteristics parameter symbol conditions min. typ. max. unit v pp setup time t psron v pp high voltage 1.0 m s v pp - setup time from v dd - t drpsr v pp high voltage 1.0 m s reset - setup time from v pp - t psrrf v pp high voltage 1.0 m s v pp count start time from reset - t rfcf 1.0 m s count execution time t count 2.0 ms v pp counter high-level width t ch 8.0 m s v pp counter low-level width t cl 8.0 m s v pp counter noise elimination width t nfw 40 ns
55 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psron t psrrf t drpsr t ch t cl t count
56 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 8. package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 - 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 - 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
57 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 20 1 s 80 pin plastic tqfp (fine pitch) (12x12) item millimeters i j 0.50 (t.p.) 0.10 a 14.00 0.20 b 12.00 0.20 c 12.00 0.20 d 14.00 0.20 f g 1.25 1.25 h 0.22 p80gk-50-be9-6 s 1.27 max. k 1.00 0.20 l 0.50 0.20 m 0.145 n 0.10 p 1.05 0.07 q 0.10 0.05 r5 5 +0.05 ?.04 +0.055 ?.045 j ns l k m detail of lead end 61 60 41 40 21 80 a b c d s qr g f p hi m note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition.
58 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f 1.25 14.0 0.2 b 12.0 0.2 m n 0.08 0.145 0.05 p q 0.1 0.05 1.0 j 0.5 (t.p.) k l 0.5 1.0 0.2 i 0.08 s 1.1 0.1 r 3 + 4 - 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u 0.6 0.15
59 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 9. recommended soldering conditions the m pd78f0058 and 78f0058y should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 9-1. surface mounting type soldering conditions m pd78f0058gc-8bt : 80-pin plastic qfp (14 14 mm) m pd78f0058ygc-8bt : 80-pin plastic qfp (14 14 mm) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-00-2 count: twice or less vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-00-2 count: twice or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) C caution do not use different soldering methods together (except for partial heating). m pd78f0058gk-be9: 80-pin plastic tqfp (12 12 mm, resin thickness 1.05 mm) m pd78f0058ygk-be9: 80-pin plastic tqfp (12 12 mm, resin thickness 1.05 mm) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-107-2 count: twice or less, exposure limit: 7 days note (after 7 days, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-107-2 count: twice or less, exposure limit: 7 days note (after 7 days, prebake at 125 c for 10 hours) wave soldering C C partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) C note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
60 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 m pd78f0058gk-9eu : 80-pin plastic tqfp (12 12 mm, resin thickness 1.0 mm) m pd78f0058ygk-9eu : 80-pin plastic tqfp (12 12 mm, resin thickness 1.0 mm) soldering soldering conditions recommended method condition symbol infrared reflow undefined undefined vps undefined undefined wave soldering undefined undefined partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) C
61 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 appendix a. development tools the following development tools are available for system development using the m pd780058, 780058y subseries. also, refer to (5) cautions on using development tools. (1) language processing software ra78k0 assembler package common to the 78k/0 series cc78k0 c compiler package common to the 78k/0 series df780058 device file for the m pd780058, 780058y subseries cc78k0-l c compiler library source file common to the 78k/0 series (2) flash memory writing tools flashpro iii (part number: dedicated flash programmer for microcontrollers incorporating flash memory fl-pr3, pg-fl3) fa-80gc-8bt adapter for flash memory writing fa-80gk fa-80gk-9eu (3) debugging tools ? when using the ie-78k0-ns in-circuit emulator ie-78k0-ns in-circuit emulator common to the 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa performance board to enhance and expand the functions of the ie-78k0-ns ie-70000-98-if-c adapter used when a pc-9800 series pc (except notebook pc) is used as the host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable used when a pc-9800 series notebook pc is used as the host machine (pcmcia socket supported) ie-70000-pc-if-c adapter necessary when an ibm pc/at tm -compatible is used as the host machine (isa bus supported) ie-70000-pci-if interface adapter necessary when using a pc with pci bus as the host machine ie-780308-ns-em1 emulation board common to the m pd780308 subseries np-80gc emulation probe for 80-pin plastic qfp (gc-8bt type) np-80gk emulation probe for 80-pin plastic tqfp (gk-be9, gk-9eu type) tgk-080sdw conversion adapter to connect the np-80gk and a target system board on which 80-pin plastic tqfp (gk-be9, gk-9eu type) can be mounted ev-9200gc-80 socket to be mounted on a target system board made for 80-pin plastic qfp (gc-8bt type) id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to the 78k/0 series df780058 device file for the m pd780058, 780058y subseries
62 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 ? when using the ie-78001-r-a in-circuit emulator ie-78001-r-a in-circuit emulator common to the 78k/0 series ie-70000-98-if-c adapter used when pc-9800 series pc (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at-compatible as the host machine (isa bus supported) ie-78000-r-sv3 interface adapter and cable used when ews is used as the host machine ie-780308-ns-em1 emulation board common to the m pd780308 subseries ie-780308-r-em ie-78k0-r-ex1 emulation probe conversion board necessary when using the ie-780308-ns-em1 on the ie-78001-r-a. ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-8bt type) ep-78054gk-r emulation probe for 80-pin plastic tqfp (gk-be9, gk-9eu type) tgk-080sdw conversion adapter to connect the ep-78054gk-r and a target system on which an 80- pin plastic tqfp (gk-be9, gk-9eu type) can be mounted ev-9200gc-80 socket to be mounted on a target system board made for 80-pin plastic qfp (gc-8bt type) id78k0 integrated debugger for ie-78001-r-a sm78k0 78k/0 series common system simulator df780058 device file for the m pd780058, 780058y subseries (4) real-time os rx78k/0 real-time os for the 78k/0 series mx78k0 os for the 78k/0 series
63 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 (5) cautions on using development tools ? the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780058. ? the cc78k0 and rx78k/0 are used in combination with the ra78k0 and df780058. ? the fl-pr3, fa-80gc-8bt, fa-80gk, fa80gk-9eu, np-80gc, and np-80gk are products of naito densei machida mfg. co., ltd. (tel: +81-44-822-3813). contact an nec distributor regarding the purchase of these products. ? tgk-080sdw is a product made by tokyo eletech corp. for further information, contact daimaru kogyo, ltd. electronics department (tokyo) (tel: +81-3-3820-7112) electronics 2nd department (osaka) (tel: +81-6-6244-6672) ? for third-party development tools, see the single-chip microcontroller development tool selection guide (u11069e) ? the host machine and os suitable for each software are as follows: host machine [os] pc ews pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at-compatible sparcstation tm [sunos tm ,solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k0 ? note ? cc78k0 ? note ? id78k0-ns ? C id78k0 ?? sm78k0 ? C rx78k/0 ? note ? mx78k0 ? note ? note dos-based software
64 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not ma rked as such. documents related to devices document name document no. japanese english m pd780058, 780058y subseries users manual u12013j u12013e m pd780053, 780054, 780055, 780056, 780058 data sheet u12182j u12182e m pd78f0058, 78f0058y data sheet u12092j this document 78k/0 series users manual - instruction u12326j u12326e 78k/0 series instruction table u10903j C 78k/0 series instruction set u10904j C 78k/0, 78k/0s series flash memory write application note u14458j u14458e documents related to development tools (users manuals) document name document no. japanese english ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly u11789j u11789e language ra78k series structured assembler preprocessor u12323j eeu-1402 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e ie-78k0-ns u13731j u13731e ie-78001-r-em to be prepared to be prepared ie-780308-ns-em1 to be prepared to be prepared ie-780308-r-em u11362j u11362e ep-78230 eeu-985 eeu-1515 ep-78054gk-r u13630j C sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator external part user open u10092j u10092e interface specifications id78k0-ns integrated debugger windows based reference u12900j u12900e id78k0 integrated debugger ews based reference u11151j C id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
65 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 documents related to embedded software (users manuals) document name document no. japanese english 78k/0 series real-time os fundamentals u11537j u11537e installation u11536j u11536e 78k/0 series os mx78k0 fundamental u12257j u12257e other related documents document name document no. japanese english semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to microcomputer-related products by third party u11416j C caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
66 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided thst the system conforms to the i 2 c standard specification as defined by philips.
67 m pd78f0058, 78f0058y data sheet u12092ej1v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m pd78f0058, 78f0058y the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8 fip and iebus are trademarks of nec corporation. windows is either a registered trademark or trademark of microsoft corporation in the united states and/ or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.

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